1. Field of the Invention
The present invention relates to a method for fabricating a highly integrated semiconductor memory device, and more particularly to a method for fabricating a semiconductor memory device, capable of obtaining a sufficient storage capacitance even when a memory cell area is reduced.
2. Description of the Prior Art
Generally, a semiconductor memory device such as a dynamic random access memory (DRAM) comprises a plurality of memory cells so as to store a large quantity of information. Each of the memory cells of the semiconductor memory device includes a capacitor for storing electric charges therein and a field effect transistor for opening and closing charge and discharge passages of the capacitor. As such since a DRAM has a higher integration degree, it is difficult to ensure a sufficient storage capacitance. This is because each memory cell of the DRAM has an abruptly reduced occupied area as the DRAM has the higher integration degree. Such a reduction in the occupied area of memory cell results in a reduction in the surface area of a storage electrode included in each capacitor. Actually, the storage electrode of each capacitor which constitutes each memory cell together with each corresponding field effect transistor is formed in the form of a plane plate shape over the field effect transistor. Due to such a shape, the storage electrode has a surface area abruptly reduced as the memory cell has a reduced occupied area. In this regard, conventional methods for fabricating memory cells have difficulties in increasing the surface area of storage electrode because they involve the formation of a storage electrode having a plane plate shape.
Referring to FIG. 1, there is illustrated a semiconductor memory device fabricated in accordance with one of the conventional methods. In FIG. 1, a semiconductor substrate 1 is shown which includes a field oxide film 2 formed on a predetermined portion of the semiconductor substrate 1, and a gate insulating film 3 and a word line 4 formed on an element region of the semiconductor substrate 1 defined by the field oxide film 2. Oxide film spacers 5 are formed on side walls of the word line 4, respectively. At exposed surface portions of the semiconductor substrate 1 defined by the oxide film spacers 5, source/drain diffusion regions 6 and 6' are formed, each of which has a lightly doped drain (LDD) structure. The source/drain diffusion regions 6 and 6' are formed by primarily implanting impurity ions in the semiconductor substrate 1 under a condition that the word line 4 is used as a mask, forming oxide film spacers on side walls of the word line 4, respectively, and then secondarily implanting impurity ions in the semiconductor substrate 1 under a condition that the oxide film spacers 5 are used as a mask. Together with the word line 4, the source/drain diffusion regions 6 and 6' constitute a field effect transistor.
Over the entire exposed surface of the resulting structure formed with the field effect transistor, an insulating oxide film 7 is coated. On the insulating oxide film 7, a storage electrode 11 is disposed which is in contact with a selected one of the source/drain diffusion regions 6 and 6'. The storage electrode 11 is formed by selectively etching the insulating oxide film 7, thereby forming a contact hole through which one of the source/drain diffusion regions 6 and 6' is exposed, forming a polysilicon layer over the entire exposed surface of the resulting structure obtained after the formation of the contact hole, and then patterning the polysilicon layer by use of a mask. On the upper surface and side walls of the storage electrode 11, a dielectric film 18 is formed using a growth process. The dielectric film 18 has a composite structure of an NO type constituted by a nitride film and an oxide film or an ONO type constituted by an oxide film, a nitride film and another oxide film. A plate electrode 19 is disposed over the entire exposed surface of the resulting structure obtained after the formation of the dielectric film 18. The plate electrode 19 is formed by forming a second polysilicon layer doped with an impurity over the entire exposed surface of the resulting structure obtained after the formation of the dielectric film 18, and then patterning the second polysilicon layer to have a predetermined dimension.
As apparent from the above description, the semiconductor device fabricated in accordance with the method of FIG. 1 has the storage electrode having the plane plate shape. Due to such a plane plate shape of the storage electrode, it is impossible to obtain a sufficient storage capacitance when the memory cell has a reduced occupied area. As a result, it is difficult for the conventional semiconductor memory device to have a high integration degree because of the insufficient storage capacitance.